1. Field of the Invention
The invention relates to a liquid crystal display (LCD) device, and more particularly, to a poly-silicon thin film transistor (TFT) array substrate and a method for fabricating the same.
2. Discussion of the Related Art
Active matrix liquid crystal display (AM-LCDs) devices are flat panel display devices widely utilized in a variety of applications, such as notebook computers, private mobile communication terminals, television (TV) sets and aircraft monitors. AM-LCDs have characteristics of low-driving voltage, full color rendering, compact size, thin profile, and lightweight due in part to the use of thin film transistors (TFTs) as switching devices. Thin film transistors (TFTs) can be broadly divided into TFTs using amorphous semiconductor films, such as amorphous silicon (a-Si), and TFTs using polycrystalline semiconductor films as an active semiconductor layer. Examples of polycrystalline silicon are poly-silicon (Poly-Si) and microcrystalline silicon (μ c-Si).
Semiconductors made of polycrystalline silicon have a carrier mobility that is 10 to 100 times greater than that of semiconductors made of amorphous silicon, so as to have excellent characteristics as an active layer for a switching device. Because the thin film transistors (TFTs) utilizing polycrystalline silicon in an active semiconductor layer can achieve high-speed operation, various logic circuits, such as CMOS-TFT (Complementary Metal Oxide Semiconductor TFT), EPROM (Erasable and Programmable Read Only Memory), EEPROM (Electrically Erasable and Programmable Read Only Memory) RAM (Random Access Memory), driving circuits of liquid crystal display (LCD) devices and driving circuits of electroluminescent display (ELD) devices use polycrystalline silicon TFTs as switching devices. The LCD device generally includes a TFT array substrate having a thin film transistor (TFT) for selective application of signals to a pixel electrode and a storage to ensure that the pixel region is maintained in the charged state until the unit pixel region is addressed by a next signal, a color filter layer array substrate having a color filter layer for realization of desired colors, a layer of liquid crystal molecules interposed between the TFT array substrate and the color filter layer array substrate, and a driving circuit for driving various elements on the two array substrates to display an image in response to external signals.
FIG. 1 is a process flow chart showing the fabrication sequence of a poly-silicon TFT array substrate according to the related art. FIGS. 2A to 2E are cross-sectional views of the process for forming a poly-silicon TFT array substrate according to the related art. FIG. 3A is a plan view of the related art poly-silicon TFT array substrate.
As shown in FIG. 2A, a buffer layer 12 of silicon dioxide (SiO2) is formed over a surface of an insulating substrate 11 using a plasma enhanced chemical vapor deposition (PECVD) method. The PECVD method is based on the principle in which plasma-excited electrons collide with gaseous compounds introduced in a neutral state to decompose the gaseous compounds. The decomposed gaseous compounds are recombined to form a thin film by assistance of the reaction between the thus-formed gas ions and the thermal energy supplied from the gas. Thereafter, a poly-silicon layer 22 is formed over the surface of the buffer layer 12 using the PECVD method or the like, as described in step S11 of FIG. 1.
Next, as shown in FIG. 2B, the poly-silicon layer 22 is patterned to form a semiconductor layer 13 by photolithography, and an inorganic material SiO2 is then deposited on the surface of the semiconductor layer 13 to form a gate insulating layer 14. Next, a low-resistance metal layer is deposited on the gate insulating layer 14 and is then patterned to form a gate line having a gate electrode 15a in one direction, as described in step S12 of FIG. 1. The gate electrode 15a is formed of one of a single metal layer of aluminum (Al) or copper (Cu), and a double metal layer having a metal stack of molybdenum (Mo), tungsten (W), chromium (Cr) or platinum (Pt) on an aluminum (Al) layer. The gate electrode 15a overlaps a predetermined region of the semiconductor layer 13.
Next, as shown in FIG. 2C, a high concentration of n-type impurity ions is doped into the semiconductor layer 13 using the gate electrode 15a as a mask to form source/drain regions 13a and 13b, as described in step S14 of FIG. 1. The semiconductor layer 13 between the source region 13a and the drain region 13b in which the impurity ions are not doped due to the shielding by the gate electrode 15a becomes a channel layer 13b. 
Then, as shown in FIG. 2D, an inorganic material such as SiO2 is deposited over the surface of the semiconductor layer 13, including the gate electrode 15a, by chemical vapor deposition (CVD), thereby forming an interlayer dielectric layer 16, as described in step S14 of FIG. 1.
Next, the surface of the semiconductor layer 13 is subjected to rapid thermal annealing (RTA), laser beam irradiation using excimer laser, or thermal annealing inside a furnace, thereby activating the semiconductor layer 13, as described in step S115 of FIG. 1. After the activation process, the gate insulating layer 14 and the interlayer dielectric layer 16 are etched to expose the source/drain regions 13a and 13b, thereby forming first contact holes 20a and 20b. To etch the gate insulating layer 14 and the interlayer dielectric layer 16, dry etching is commonly carried out.
Next, as shown in FIG. 2E, a low-resistance metal layer is deposited on the interlayer dielectric layer 16 and is then patterned to form a data line perpendicular to the gate line and having source/drain electrodes 17a and 17b, which are in contact with the source/drain regions 13a and 13b, respectively, as described in step S16 of FIG. 1. The source/drain electrodes 17a and 17b are formed of one of a single metal layer of aluminum (Al) or copper (Cu), and a double metal layer having a metal stack of molybdenum (Mo), tungsten (W), chromium (Cr) or platinum (Pt) on an aluminum (Al) layer. As a result of the above-described process steps, a poly-silicon thin film transistor is formed having an active semiconductor layer 13 utilizing poly-silicon.
Next, an inorganic material, such as silicon nitride (SiNx), is deposited over the poly-silicon thin film transistor, including the source/drain electrodes 17a and 17b, thereby forming a passivation layer 18, and then the substrate is heated to a range of heat resistance temperature thereof to perform a hydrogenation process, which diffuses hydrogen atoms contained in the passivation layer 18 into the polycrystalline semiconductor layer 13, as described in step S17 of FIG. 1.
Subsequently, the passivation layer 18 is selectively removed so as to expose the drain electrode 17b, thereby forming a second contact hole 40, and a pixel electrode 37 on a pixel region in such a manner that the pixel electrode 37 is in contact with the drain electrode 17b via the second contact hole 40 (S18).
The related art poly-silicon TFT array substrate and a method for fabricating the same employ an exposure mask at least 6 times for formation of a semiconductor layer, a gate line layer, first contact holes, a data line layer, a second contact hole, and a pixel electrode. Using exposure masks six times results in complicated processes that increase process time and process costs while lowering process efficiency. Further, exposure equipment is expensive. Therefore a great deal of study has been continuously made to omit process steps that involving use of the exposure equipment.
A method has been proposed which involves co-patterning of the semiconductor layer and the gate line layer by application of a diffraction exposure. When the semiconductor layer and the gate line layer are concurrently patterned by the diffraction exposure, as shown in FIG. 3, below the gate line 15 and the gate electrode 15a, the semiconductor layer 13 is disposed in the same pattern as the gate line and the gate electrode, and extends over the right/left sides of the gate electrode 15a. The semiconductor layers on the right/left sides of the gate electrode become the source and drain regions, respectively. In such a pattern, a data voltage applied to a first sub-pixel through the data line 17 should flow to be charged to a pixel electrode 19 of the first sub-pixel through a thin film transistor of the first sub-pixel (Route {circle around (1)}), but the data voltage flows to be charged through the semiconductor layer disposed below the gate line to a pixel electrode of a second sub-pixel adjacent to the first sub-pixel (Route {circle around (2)}), thereby resulting in a problem of signal distortion.